Divide-By-Odd-Number Counter

  
This circuit symmetrically divides an input by virtually any odd number. The circuit contains n + 1h clocks tw
Divide-By-Odd-Number Counter - schematic

ice to achieve the desired divisor. By selecting the proper n, which is the decoded output of the 74LS161 counter, you can obtain divisors from 3 to 31. This circuit divides by 25; you can obtain higher divisors by cascading additional LS161 counters. The counter and IC5A form the n + ll-z counter. Once the counter reaches the decoded counts, n, IC5A ticks off an additional 1h clock, which clears the counter and puts it in hold. Additionally, IC5A clocks IC5B, which changes the clock phasing through the XOR gate, IC1. The next edge of the input clocks IC5A, which reenables the counter to start counting for an additional n + 1/2 cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis reveals that the maximum input frequency is between 7 and 8 MHz.




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