Phase Shifter

This circuit adds 120 degrees of phase shift to a 50- or 60-Hz input, regardless of the frequency and amplitude fluctuations
Phase Shifter - schematic

of that input. The circuit configures a 2N4093 JFET as a voltage-controlled resistor whose value is proportional to the phase difference between the input and the output. The values of Q, Ri, and r^s determine the amount of phase shift (120° this case.) A 555 timer implements a phase detector whose two inputs are related to the input and output. The input and output, respectively, drive IC1B and IC1C, which operate as zero-crossing detectors. D1 and D2 limit the positive-going pulses at the 555 inputs. Thus, the falling edges of IC1B and IClC"s outputs control the 555 timer. The timer"s output signal stays low for a time that is proportional to the phase shift between the circuit"s input and output. The average value of the timer"s output and an offsetting voltage drive IC1D. R2 and C2 filter IClD"s output. The resultant signal controls the JFET. The potentiometer sets the control at a value for which the phase shift between input and output is equal to 120 degrees when the input signal frequency is 50 or 60 Hz. Any differences between the input and output changes the 555 output"s average value, thus ultimately modifying the control voltage and the JFET"s resistance. To calibrate the circuit, apply a 50-Hz sine wave with an amplitude of less than 1 Vpp to the input and adjust the potentiometer until the phase shift reads 120° on a digital phase meter. For input frequency variations between 40 and 60 Hz, the phase shift changed by a maximum of ±0.17% (equivalent to an offset of only 0.02°/Hz). The average value at IClD"s noninverting input is 3.864 V.

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