Non-integer-programmable-pulse-divider


Posted on Apr 23, 2012

The purpose of D-type flip-flop IC2 is to synchronize the input signal with the clock pulse. When the clock pulse changes from low to high and the input is high, IC2 output is high. Subsequently, IC3 resets to zero and starts counting up. Until the counter counts to ten, the counter is inhibited. Thus, the number of pulses of the output of IC3 is ten times input pulse. The designed frequency of the clock pulse must be ten times higher than the maximum frequency of the input.


Non-integer-programmable-pulse-divider
Click here to download the full size of the above Circuit.

IC4 and IC5 are cascaded to form a two decade programmable down counter. Since the number of pulses appearing at the input of the down counter is ten times the input to the divider, the effective range of the divisor for this divider is 0.1 to 9.9.




Leave Comment

characters left:

Related Circuits

  • New Circuits

    .

     


    Popular Circuits

    Bi-directional motor control
    Precision current sink
    5 DOT LED LINEAR LEVEL METER DRIVER
    Oscillator Design Guide Structure
    Design and simulation study of anti exciting type switching power supply of single-end
    Triangle/Square-Wave Oscillator Serves Dual Purpose
    mbed usb breakout
    Smiths Tachometer
    EPROM adapter for ATMEL 89 Series Flash Microcontroller Programmer
    Giving a false speed reading
    555 multi-temperature test circuit configuration
    High and low frequency signal generator circuit diagram
    Output by the CS3843 and CS5101 composed of 5V 3.3V switching DC power supply circuit



    Top