In a basic astable timer, configuration timing periods 11 and 12 are not controlled independently. The lack of control makes it difficult to maintain a constant period, T, if either 11 or 12 is varied. In this circuit, charge RAB and discharge R8 c resistances are detenriined by the position of common wiper arm~ of the potentiometer. So, it is possible to adjust the duty-cycle by adjusting 11 and 12 proportionately, without changing period T.
Variable-duty-cycle-oscillator - schematic

At start-up, the voltage across C, is less than the trigger level voltage ("12 VDD). causing the timer to be triggered via pin 2. The output of the timer at pin 3 increases, turning off the discharge transistor at pin 7 and allowing C, to charge through diode Dl and resistance RAB· When capacitor C1 charges to upper threshold voltage 213 VDD. the flip-flop is reset and the output at pin 3 decreases. Capacitor C, then discharges through diode D2 and resistor R8c. When the voltage at pin 2 reaches 1/3 VnD, the lower threshold or trigger level, the timer triggers again and the cycle is repeated. In this circuit, the oscillator frequency remains fixed and the duty cycle is adjustable from less than 0.5% to greater than 99.5%.

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