SYNTHESIZER BASICS

This is a programmable frequency multiplier that typically utilizes digital logic integrated circuits. The synthesizer is designed to multiply a reference frequency by a programmable factor to achieve virtually any desired frequency. For instance, with a reference frequency of 1 kHz and a programmable multiplier, it is possible to generate frequencies such as 1 kHz (X1), 3 kHz (X3), 1.025 MHz (X1025), 98.325 MHz (X98325), or any other frequency as needed. While this may seem straightforward, it becomes easier with an understanding of the underlying principles. The construction of a simple synthesizer capable of covering frequencies from 3 kHz to 4 MHz involves a Phase Locked Loop (PLL), which includes a Voltage Controlled Oscillator (VCO) whose output frequency is monitored and adjusted. An error voltage is produced to guide the VCO back to the correct frequency. This error voltage is generated by a Phase Sensitive Detector (PSD) that compares the VCO frequency with a reference frequency. In the proposed block diagram, a 1 kHz reference oscillator is connected to the PSD Input-B, while the VCO is connected to the PSD Input-A. The output of the PSD can be a square wave, and the average difference between the positive and negative pulses is processed by a low-pass filter (LPF). This filtering results in a DC voltage that is fed back to the VCO to adjust the frequency as needed. It is noteworthy that a DC voltmeter can be connected to the DC control line to observe voltage variations, which will occur if either the VCO center frequency or the reference frequency changes. This circuit can be constructed using a single CD4046, excluding the reference oscillator. The reference oscillator input can be connected externally to accommodate various useful instruments. The PSD signal input of the CD4046 is quite sensitive, requiring only a few hundred millivolts of input signal at pin 14. It is DC self-biasing, allowing for the use of a capacitor in series with the low-level input signal. For more detailed information about the CD4046, the CD4046 datasheet should be consulted. Any two-input logic gate can function as a PSD, with the OR gate or EXCLUSIVE-OR gate being the most common choices. When using an EXCLUSIVE-OR gate, the output frequency will be double the input frequency, although the mark-space ratio will vary based on the phase difference between the two input signals. When the loop is "in lock," there will be approximately a 90-degree phase difference between the input signals. This type of PSD is effective, economical, and straightforward. However, a drawback is that if the input frequencies differ, the output mark-space ratio will fluctuate continuously, which may hinder the loop's ability to achieve a lock. If the natural frequency of the oscillator in the aforementioned circuit is less than about 750 Hz or greater than approximately 1.35 kHz, it will not achieve a lock condition. The capacity to capture the VCO is quantified as the top and bottom VCO frequencies that can be captured, expressed as a ratio known as the capture ratio. A typical capture ratio for this type of detector is about 2:1, which is considered inadequate, yet it allows the loop to lock onto harmonics of the VCO. A more advanced type of PSD can be constructed using four Master/Slave J-K Flip-Flops, arranged to provide a permanent HIGH (1) output when the reference frequency exceeds the VCO frequency.

The programmable frequency multiplier described utilizes a Phase Locked Loop (PLL) architecture, which is a fundamental component in frequency synthesis. The PLL operates by continuously comparing the output frequency of the VCO to a stable reference frequency, adjusting the VCO output to minimize the phase difference between the two signals. The Voltage Controlled Oscillator (VCO) is a critical element that generates frequencies based on an input control voltage. The design typically includes a low-pass filter (LPF) to smooth out the error voltage generated by the Phase Sensitive Detector (PSD), ensuring a stable control voltage for the VCO.

In practical applications, the choice of the reference oscillator is crucial, as it determines the precision and stability of the synthesized frequency. The CD4046 integrated circuit provides a versatile platform for implementing PLL designs, featuring built-in functionality for phase detection and VCO operation. The PSD can be implemented using various logic gates, with the EXCLUSIVE-OR gate being particularly advantageous due to its sensitivity to phase differences.

The capture range of the PLL is an important specification, indicating the frequency range over which the loop can successfully lock onto the VCO. A capture ratio of 2:1 is typical for basic designs, but more sophisticated configurations can achieve better performance by utilizing advanced phase detection techniques, such as those employing J-K Flip-Flops. These configurations improve the loop's ability to maintain lock even in the presence of significant frequency deviations, enhancing overall performance and stability in frequency synthesis applications.

Overall, this programmable frequency multiplier circuit serves as a foundation for various applications in communication systems, signal processing, and other electronic devices requiring precise frequency generation and control.It is a programable frequency multiplier, usually using digital logic integrated circuits. The synthesizer is aranged to multiply a reference frequency by a programable amount to achieve just about any frequency you want. If, for example you had a reference frequency of, say, 1KHz and a "programable multiplier" then you could program the multiplier to give you

1KHz (X1), 3KHz (X3), 1. 025MHz (X1025), 98. 325MHz (X98325) or any other frequency you want. Sounds easy Actually, it is so easy, once you understand some of the basics. So let us start off by building a simple synthesizer that cover 3KHz to 4000KHz (4MHz). A Phase Locked Loop (PLL) consists of a Voltage Controlled Oscillator (VCO), the output frequency of which is monitored and controlled. An error voltage steers the VCO and brings it back onto the correct frequency. The error voltage is generated by a Phase Sensitive Detector (PSD) which compares the VCO frequency with a reference frequency.

Consider the following block diagram: Here we have a 1KHz reference oscillator feeding the PSD Input-B, and a VCO feeding the PSD Input-A. The output of the PSD can be a square-wave and the difference between the positive pulse and the negative is averaged by the low-pass filter (LPF).

This filtering results in a DC voltage that is fed back to the VCO to increase or decrease the frequency, as required. It is interesting to note that you can put a DC voltmeter on the DC control line and watch the DC vary.

The voltage will vary if either the VCO centre-frequency changes or the reference frequency changes. This circuit alone can be built using a single CD4046, but without the reference oscillator. The reference osc input can then be an external connection to make a selection of usefull instruments, such as: The PSD signal input of the CD4046 is quite sensitive and only requires a couple of hundred millivolts of input signal to pin 14. It is DC self-biasing so all you need to do is stick a capacitor in series with your low-level input signal.

For more detailled information about the CD4046 then take a look at the CD4046 Datasheet (pdf format). Almost any logic 2-input gate can be used as a PSD, but the more usual is a simple OR- gate or an EXCLUSIVE-OR-gate.

With an EXCLUSIVE-OR gate the output frequency will be twice the input frequency, but the MARK:SPACE ratio will vary as the phase between the two input signals. When the loop is "IN LOCK" there will be about 90-degrees phase difference between the two input signals.

This sort of PSD is good, cheap and simple. One drawback of it is that if the two inputs are of different frequencies then the output MARK:SPACE ratio will go continuously up and down. This will restrict the ability of the loop to achieve a lock. If the natural frequency of the oscillator in the circuit above were to be less than about 750Hz or greater than about 1.

35KHz then it would never achieve a lock condition. This ability to capture the VCO is measured as the top and bottom VCO frequencies that can be captured, expressed as a ratio and know as the CAPTURE RATIO. A typical capture ratio for this type of detector is just 2:1 (piss-poor) and it will even allow the loop to lock on harmonics of the VCO.

A much nicer type of PSD is composed of four Master/Slave J-K Flip-Flops in an arrangement that will deliver a permanent HIGH (1) when the reference frequency is higher than the VCO frequency. 🔗 External reference