MFOS Micro-Sample & Hold circuit

Posted on Feb 6, 2014

Voltage to be sampled is applied to the input which is one end of R2 (100K linear taper potentiometer). The other end of R2 is grounded and thus the level of signal applied to buffering level shifter U1-A and associated components is controlled by R2. Signals applied to the sample and hold (at point X1) can oscillate about ground but should not exceed

MFOS Micro-Sample & Hold circuit
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about +/-5. 5 volts. That is why the design was changed to allow for higher level signals since they can be attenuated by adjusting R2. If the voltage at pin 1 of U1-A goes below ground Q1 can clip the signal and improper sampling results. R1 and R3 comprise a voltage divider which causes the applied attenuated signal to be effectively cut down to half of it`s level. This signal is applied to U1-A (1/4 LF444 quad op amp) where it is level shifted and given a gain of about 1. 5. Here you can see the comparison of the input signal to the signal at pin 1 of U1-A. Q1 N-Channel JFET 2N5457 acts like a closed switch (between source and drain) when it`s gate is brought slightly above ground by differentiated pulses which are generated by picking off the front end of the rectangle wave output by U1-D sample clock generator. Normally (when no pulse is being applied) the gate of Q1 is held at about -3. 6V by resistor network R7, R6 and R13. The voltage that is present at the source of Q1 passes through to the drain and charges (or discharges as the case may be) C1 where the sampled voltage is held until the next pulse hits the gate. U1-B buffers the sample held on the cap. The LF444CN chip has ultra low input current which allows the sample to sit on the cap and be buffered by U1-B for quite some time. With no pulse applied to the gate of Q1 it essentially acts like an open switch (source to drain) and the voltage on C1 does not...

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