The two input boards ( ADCV or digital ) get connected to AD_CTL1, AD_DATA1, AD_SUP5V_1, AD_SUP3V3_1 for the first board and the same names with suffix 2 for the second board. To transfer the sampling data, the 16 digital data lines from the two input boards are fed into the 16bit wide bus of the FX2-USB board (USB_PA, ). Each input board can have
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up to 3 control lines (pins 1, 2 and 4 of AD_CTL) which are set from the USB-FX2 board`s 8051 controller via lines USB_PA1, 3, 7 and shift register IC2. IC1A, B form together an RS-flip-flop which was meant to detect FIFO buffer overflows (i. e. when the USB-FX2 board is not able to transmit data over the USB fast enough). It is connected to the clock generator so that it can take action. However, this feature currently is not used at all and the FIFO stall can probably also be detected by a software interrupt in the FX2. IC1C, D to the necessary clock inversion because ADCV clock and interface clock need to be inverted compared to the latch clock. (See also the waveform diagrams on the schematic. )
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