Posted on Jul 18, 2012

This circuit extracts the sync pulses from a video signal over a wide range of amplitudes and operates a single +15 V supply. IC1 buffers and amplifies the incoming signal and applies it via C3 to the peak detector, consisting of D2 and C4. It is also applied to one input of a comparator, IC2. The other input of IC2 is set at a voltage corresponding to about 0.065 of the peak video amplitude, by the divider R4/R5.

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The trigger points of IC2 are set near the bottom of the sync pulses which help prevent spurious noise. These resistors also leak across C4, so they must be chosen as a compromise he tween excessive ripple and speed of response to falling signal levels. The IC2 output swings between 0 and 15 V and is conveniently CMOS compatible, but further buffering is advisable, hence the CMOS inverter. Maximum input amplitude is set by saturating IC1"s output. The minimum acceptable level is set by the forward voltage drop of the de restoring clamp D1, which should be either a germanium (as shown) or a Schottky diode.

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