Digital capacitance meter

The principle of operation is counting the pulse number derived from a constant frequency oscillator during a fixed time interval produced by another lower frequency oscillator. This oscillator uses the capacitor being measured as the timing. The capacitance measurement is proportional during pulse counting during a fixed time interval. The astable oscillator formed by IClc produces a pulse train of constant frequency. Gate ICla also forms an oscillator whose oscillation period is given approximately by the equation: T = 0.7 RC.
Digital capacitance meter - schematic

Period ? is linearly dependent on the capacitance C. This period is the time interval for one measurement. The differentiator network following the oscillator creates the negative spikes shaped in narrow pulses by IClb NAND Schmitt Trigger. The differentiator formed by Rl and CI produces a negative spike which resets the counters. The display shows the number of high frequency oscillator pulses entering the counter during the measurement period.

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