The 5-MHz track and hold shown here has a 400-kHz power bandwidth driving ±10 V. A buffered input follower drives the hold capacitor, C4, through Ql, a low resistance FET switch. The positive hold conuuand is supplied by TTL logic, with Q3Ievel shifting to the switch driver, Q2. The output is buffered by A3. When the gate is driven to V-for hold, it pulls the charge out of the hold capacitor. A compensating charge is put into the hold capacitor through C3. The step into hold is made independent of the input level with R7, and adjusted to zero with RIO.
Track-and-hold - schematic

Since internal dissipation can be quite high when driving fast signals into a capacitive load, using a buffer in a power package is reconuuended. Raising the buffer quiescent current to 40 mA with R3 improves frequency response.

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