Pulse Generator

This circuit is quite effective for testing or operating counters and stepping relays, as it eliminates the need for manually setting a switch for the desired number of pulses. By pressing the appropriate switches S1 to S9, one can generate 1 to 9 negative-going clock pulses, respectively. The Schmitt trigger NAND gate N1 of IC2, along with resistor R1 and capacitor C1, is configured to produce clock pulses. These pulses are output through NAND gate N3, which is controlled by the decade counter CD4017 (IC1). Initially, when no switch from S1 to S9 is pressed, the LED is illuminated. Since pins 5 and 6 of NAND gate N2 are pulled high by resistor R3, its output pin 4 goes low, disabling NAND gate N3 from driving its output pin 10 high, resulting in no available pulses. IC1 is a decade counter with Q outputs that typically remain low. When clock pulses are applied, the Q outputs transition high successively, meaning Q0 shifts to Q1, Q1 shifts to Q2, Q3 shifts to Q4, and so forth. If any one of the switches S1 through S9 is briefly pressed, for example, S5 for five pulses, pins 5 and 6 of NAND gate N2 will go low, causing output pin 4 to go high, which fully charges capacitor C2 through diode D. Simultaneously, this high output from N2 enables NAND gate N3, allowing clock pulses to be output through pin 10. These pulses are used to verify the operation of the device. The clock pulses are then fed to the clock-enable pin 13 of IC1, initiating the counting process. Once output pin 1 (Q5) of IC1 becomes high, input pins 5 and 6 of NAND gate N2 will also be driven high via switch S5, as the high-frequency clock permits five pulses during the momentary press. This high input to N2 results in a low output at pin 4, disabling NAND gate N3 and stopping any further pulses from advancing counter IC1. Before subsequent use, counter IC1 must return to a standby state, requiring that the Q0 output be high. A time-delay pulse generator, constructed around NAND gate N4, resistor R4, diode D, capacitor C2, and a differentiator circuit with components C3 and R5, is employed for this purpose. When output pin 4 of NAND gate N2 is low, capacitor C2 discharges gradually through resistor R4. Once the voltage across capacitor C2 falls below the lower trip point, output pin 11 of NAND gate N4 switches high, producing a sharp high-going pulse at the junction of capacitor C3 and resistor R5. This pulse resets counter IC1, bringing its Q0 output (pin 3) high, which is indicated by the illumination of the LED. The red LED should be glowing before attempting to obtain the next pulse. Pressing any of the switches momentarily will cause the LED to light up. However, if the switch is held down, the counter will continue counting continuously, preventing the acquisition of an exact number of pulses.

The circuit employs a decade counter (CD4017) to sequentially count clock pulses generated by a Schmitt trigger NAND gate configuration. The use of a Schmitt trigger ensures clean transitions of the clock signals, minimizing the effects of noise and bouncing that can occur with mechanical switches. The configuration of the NAND gates allows for a simple yet effective method of pulse generation and counting.

The time-delay pulse generator is critical for resetting the counter after operation, ensuring that the system is ready for the next cycle. The differentiator circuit composed of capacitor C3 and resistor R5 is particularly important as it generates a sharp pulse that resets the counter, allowing for reliable operation in subsequent uses.

Overall, this circuit design is efficient for applications requiring precise pulse generation and counting, making it suitable for various testing and operational tasks in electronics. The inclusion of visual indicators, such as the LED, enhances usability by providing immediate feedback on the system's state, ensuring that the operator can easily verify the readiness of the circuit before initiating further operations.This circuit is very useful while checking/operating counters, stepping relays, etc. It avoids the procedure of setting a switch for the required number of pulses. By pressing appropriate switches S1 to S9, one can get 1 to 9 negative-going clock pulses, respectively. Schmitt trigger NAND gate N1 of IC2, resistor R1, and capacitor C1 are wired to produce clock pulses. These pulses are taken out through NAND gate N3 that is controlled by decade counter CD4017 (IC1). Initially no switch from S1 to S9 is depressed and the LED is glowing. As pins 5 and 6 of NAND gate N2 are pulled up by resistor R3, its output pin 4 goes low. This disables NAND gate N3 to take its output pin 10 to high state, and no pulse is available. IC1 is a decade counter whose Q outputs normally remain low. When clock pulses are applied, its Q outputs go high successively, i. e. Q0 shifts to Q1, Q1 shifts to Q2, Q3 shifts to Q4, and so on. If any one of switches S1 through S9, say, S5 (for five pulses), is momentarily depressed, pins 5 and 6 of NAND gate N2 go low, making its output pin 4 high, which fully charges capacitor C2 via diode D. At the same time, this high output of N2 enables NAND gate N3 and clock pulses come out through pin 10.

These are the required number of pulses used to check our device. The clock pulses are fed to clock-enable pin 13 of IC1, which starts counting. As soon as output pin 1 (Q5) of IC1 turns high, input pins 5 and 6 of NAND gate N2 will also become high via switch S5 because high-frequency clock allowed five pulses during momentary pressing. This high input of N2 provides low output at pin 4 to disable NAND gate N3 and finally no pulse will be available to advance counter IC1.

Before the next usage, counter IC1 must be in the standby state, i. e. Q0 output must be in the high state. To do this, a time-delay pulse generator wired around NAND gate N4, resister R4, diode D, capacitor C2, and differentiator circuit comprising C3 and R5 is used. When output pin 4 of NAND gate N2 is low, it discharges capacitor C2 slowly through resistor R4. When the voltage across capacitor C2 goes below the lower trip point, output pin 11 of NAND gate N4 turns high and a high-going sharp pulse is produced at the junction of capacitor C3 and resistor R5.

This sharp pulse resets counter IC1 and its Q0 output (pin 3) goes high. This is represented by the glowing of LED. Ensure the red LED is glowing before proceeding to get the next pulse. Press any of the switches momentarily and the LED will glow. If the switch is kept pressed, the counter counts continuously and you cannot get the exact number of pulses. 🔗 External reference