The circuit in Figure 1 is that of a 4-bit asynchronous counter, also known as a `ripple counter`. It consists of 4 J-K flip-flops whose J and K inputs are tied to logic `1`. This connection causes the output of each J-K flip-flop to toggle every time it gets a clock pulse. By using the output of the previous flip-flop to clock the next flip-flop,

The material is presented in a manner suitable for a teaching tool. It seeks to enlighten and to spark off interest in the design of counters. As R. S. S Obermann remarks ". design of counters has, in my experience, always been an excellent proving ground for anyone who has mastered Boolean algebra. Have fun reading ! A synchronous binary counter

Asynchronous counter shown, this circuit no clock synchronization signal can be used in a random counter or independent unit circuit.