8-Digit up-down counter


Posted on Jul 15, 2012

This circuit shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked.


8-Digit up-down counter
Click here to download the full size of the above Circuit.

the Q output of the flip flop goes high and turns on the npn transistor, thereby inhibiting leading zero blanking on the low order counter.




Leave Comment

characters left:

New Circuits

.

 


Popular Circuits

Butler aperiodic oscillator
Power-line frequency meter
4-18Mhz-converter
Voltage Monitor Circuit
DS18B20
555 timer mono stable one shot circuit
improved vibrating battery
Citation I and IV phono schematic query
SQUARE WAVE GENERATOR EMBEDDED C
TTL NAND and AND gates
Power audio amplifier schematics with Tda2005
weather car wont start and radio keyless entry power windows
Railway circuits
555 capacitance tester circuit diagram
The basic structure of the DA conversion circuit multiplexer



Top