The timer includes an oscillator and a counter in an integrated circuit. The timing interval equals the oscillator period multiplied by the number of cycles to be counted. The oscillator frequency depends upon resistor RS and capacitor CX. The number of oscillator cycles to be counted before the counter output changes state is determined by the selection of the counter output terminal, shown here as pin 3. The interval can be set anywhere in the range from fractions of a second to months; it is given by = 0.55 RsCx2n, where is an integer determined by the counter-output selection. Operation is initiated by the closure of momentary switch SI (or by a command signal having a similar effect).
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This grounds one side of relay Kl, thereby activating the relay and causing the closure of the switches that supply power to the timer and to the load. The turn-on of Vcc at the timer is coupled through Cl to the counter-reset terminal, thus resetting the counter. The initial reset voltage transient is then drained away through Rl to permit normal operation. During the first half cycle of the counter operation, the counter output voltage (at pin 3 in this case) is low. This turns on transistor Ql so that relay K1 latches on, enabling the timer to continue running even though switch SI has opened. The oscillator runs while the relay is on. When the number of oscillator cycles reaches the limit, the counter output voltage at pin 3 goes high. This turns off Ql, thereby turning off the relay and returning the system to the original' 'power-off" state to await the next starting command. The timing cycle can also be interrupted and the system turned off by opening normally-closed switch S2.
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