op amp Why do some of my IE converter circuits have a large offset voltage

The inverting input is maintained at a low level via a 10K resistor when the circuit is powered on but not in use. During measurement activities, including calibration measurements where the input is floating, this resistor is disconnected. The circuit is designed to measure currents in the nanoamp range, where even a few millivolts on the output are significant. Constant offsets are manageable, as they can be calibrated out by measuring the output with an open input and subtracting that from future measurements. SW1A and SW1B represent different poles of the same CMOS switch (ADG1236), which are activated together to select the feedback resistor that determines the gain of the converter. The maximum leakage current at the source and drain pins is 1 nA, regardless of whether the switch is on or off. The switch responsible for holding the inverting input low through a 10K resistor exhibits comparable performance, with typical leakage currents being very low (< 0.1 nA). An issue arises in some batches of boards where some or all circuits exhibit large offsets that decay slowly when powered on. Conversely, most boards remain stable with minor offsets. Affected boards, upon power-up, show offsets that gradually stabilize to approximately 5 mV over hours or days. Once power is removed, the offset accumulates again, leading to a high offset when the board is powered on after being off for a couple of days. Each board contains multiple circuits, and in the first batch of five boards, all were affected. In the subsequent batch, none were affected, while the latest batch has one affected circuit per board, though it varies. In the worst-case scenario, the maximum leakage currents of all analog switches could result in a 12 mV offset at the highest gain setting, indicating that this cannot fully account for the observed offsets.

The circuit employs a feedback mechanism to stabilize the inverting input, ensuring accurate current measurements in the nanoamp range. The use of a 10K resistor allows for a defined low state when the circuit is idle, preventing noise and ensuring stability. The ADG1236 CMOS switch facilitates precise control over the feedback resistor selection, which is crucial for setting the gain of the current measurement circuit. Given the sensitivity of the application, the low leakage currents of the switches are paramount; however, variations in performance across different production batches have led to inconsistencies in offset behavior.

The phenomenon of slow-decaying offsets on certain boards may be attributed to several factors, including potential variations in the manufacturing process, differences in component tolerances, or PCB layout issues that could introduce additional parasitic capacitances or resistances. The calibration process, which relies on measuring the output with an open input, is an effective method for mitigating constant offsets; however, the persistent accumulation of offsets upon power cycling suggests that the underlying issue may not be solely related to the operational characteristics of the switches.

Further investigation into the affected boards may involve detailed analysis of the PCB layout, examination of the power supply stability, and testing of individual components to identify any anomalies. Additionally, implementing a more robust calibration routine or exploring alternative switch technologies with even lower leakage currents may help to enhance the stability and reliability of the circuit across all production batches.The inverting input is held low through a 10K resistor when the circuit is powered on but not being used. Whenever a measurement is being made (including calibration measurements where IN is floating), that resistor is disconnected.

The circuit is used to measure currents in the nanoamp range. A few mV on the output is significant. Constant offsets are not really a problem, as they can easily be calibrated out by measuring the output with an open input and subtracting that from subsequent measurements. SW1A and SW1B are different poles of the same CMOS switch (ADG1236). They are switched together to select the feedback resistor, which determines the gain of the converter.

The maximum leakage current is 1 nA on source and drain pins, on or off. The switch not shown (for holding the inverting input low through a 10K resistor) has similar performance. Typical leakage currents are very small (< 0. 1nA). The problem I am having is that in some batches of boards, some (or all) of these circuits have large offsets which decay slowly when powered on.

However, most boards are perfectly stable at all times, with small offsets. When the afflicted boards are powered on, the offset will slowly (after hours of days) stabilize to ~5 mV. After power is removed, the offset accumulates again, so when powering it on after a couple days of being off, it`s high again.

Each board has a bunch of these circuits on it. In the first batch of 5 boards, all of them were affected. In the next batch, none were affected. In the most recent batch, each board has one affected circuits, and it isn`t always the same one. At the worst case, the maximum leakage currents of all the analog switches would be 1. 2nA, resulting in a 12 mV offset at the highest gain setting, so I don`t think that can account for all the offset I`m seeing. 🔗 External reference