High-speed control scheme LED display screen circuit diagram and principle

This is a high-speed control scheme LED display screen circuit theory. Adopt the MCS51 series one-chip computer to control LED display screen; The random access memory 62512 is used as the data storage of LED display screen, store the matrix data waiting to reveal the content; Adopt 8 lines of scanning modes, the dot matrix of lamellar LED is a

scene of sharing and a group driving circuit; Each slice of LED dot matrix slice has a series of lines of driving circuit, use 74LS377 As listing the latch that is driven, CPU writes the matrix data to the latch which lists the driving circuit through the parallel bus; The decoder circuit of the address, used for producing LED dot matrix slice walking driving circuit and chip selection address which lists the driving circuit. There are two characteristics of this scheme: First, though CPU still gives and lists the latch of the driving circuit and writes the matrix data through the parallel bus, but the latching the control signal RD that the signal uses CPU instead, but not WR of the regular usage of the latch; Second, address decoder circuit guaranteed LED dot matrix a chip selection address which lists the driving circuit and logic address of some segment of the data storage are eclipsed, but not regular usage, these two group addresses must be separated. Because above-mentioned some of circuit change briefly, one-chip computer take place obvious change to the intersection of LED and the intersection of presentation control and efficiency of display screen. The concrete working phase is as follows: Having already packed into the address of the data storage while assuming the indicator DPTR of the data, execute instruction  MOVXA, @DPTR . The function of this order is CPU, according to pointing to reading the matrix data...

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