CD4011 dual-produced sound and light control delay lamp circuit

Posted on Mar 28, 2007

Sound with CD4011 digital circuits made light lamp dual-control delay section circuit shown in Figure 3-17, the left portion of the dashed line in Fig general

CD4011 dual-produced sound and light control delay lamp circuit
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lighting lines, the right part is the sound and light control delay switch double circuit, SCR vs constitute lighting the main circuit switch, the control loop is two-input NAND gate CD4011 constitute four. NAND gate I composed a linear amplifier for amplifying the audio signal B microphone input. NAND gate II composed of light control switch, the NAND gate III, t composition monostable circuit. And NAND gate logic functions are: "See 0 1, all the l O". Daytime indoors light line is strong, light-sensitive resistors RO irradiated by light exhibits low resistance, so that the NAND gate II - inputs 13 feet low level "0", the output terminal II pin is high "l", it is 9 feet also as "l". t two NAND gate inputs 5,6 feet because Rl0 ground to the low level "0", the nozzle output pin 4 is "1", 8 feet to "1." NAND gate III both inputs are "l", the output terminal IO pin to "0", low capacitance c5 both ends can not be charged, and the transistor VT due to the high base resistor R9 connected electrically and a half feet 4 Therefore VT conduction, vs VT gate is grounded off, lights are not bright. Since 13 feet low "o", so regardless of their 12 foot level changes, electronic switches are sealed bad E, the lamp can not be lighted. In the evening, photoresistor RG light irradiation exhibit a high resistance, the resistance is much greater than R8, so] 3 feet high "l", which provided the conditions for the lights, but the output of 1 l foot level 12 foot level depends on the level of the case. When someone walking, pick up sound signal by B cz coupling into the NAND I zoom in, and then by R6 to C4 (charging time constant minimum) + 12 feet so that becomes a high level "l", in accordance with NAND gate "out of whole l 0" logic. II pin output low level "0", 9 feet for the "O". From "See the 1 O" shows that IO pin is "l" that is 10 feet high output, the Rl0 to c5 charge. Root According to the principle of voltage across the capacitor is not mutated, 5,6 feet for the "l", so the output terminal 4 feet low "O", VT deadline, SCR vs the door to get forward by VD1 and Rl Ji opened contact current, lamp H powered light. After about 30 seconds, c5 is fully charged, 5,6 feet returns low "O", 4 feet high output "l", VT hunt through, vs lose touch sent electric current when the AC zero crossing that off off, lights off. At steady state, 10 feet low "0", c5 by Rl0 discharge, ready for the next turn on the lights for the delay. VD2, VD3, R2 and C6 form resistance voltage half-wave rectified line voltage, the output is about 6V DC, for the integrated circuit electricity.

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