Frequency Divider

This circuit will divide the frequency of a TTL compatible square wave signal by a factor from 0 to 999. The circuit comprises three decade counters IC1 to IC3 and a few NAND gates. The three 7490?s are cascaded and count is the input signal. When the desired and count reached all the inputs of IC4 become high, so the output goes low. This triggers the monostable consisting of IC5B and IC5C, which provides a sort output pulse. The output of IC5A goes high, resetting the three counters and the count then begins again. To program the counter it is first necessary to work out the binary coded decimal (BCD) equivalent of the required division ratio.
Frequency Divider - schematic

In the example shown the division ratio is 569. The unused inputs of IC4 are connected to +5V via a 1K resistor. Note that the circuit will not divide by 777, since this would require 9 inputs to IC4 and only 8 are available. R1=680 ohms C1=100pF ceramic IC4=7430 R2=1 Kohms IC1-2-3=7490 IC5=7400

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