Bug Detector Circuit

  
The circuit, built around a single integrated circuit (Ul, an MC3403P quad op amp), three transistors (Q1-Q3), and a few support components,.receives its input from the antenna (ANT1). The signal is fed through a high-pass filter, formed by CI, C2, and Rl, which eliminates bothersome 60-Hz pickup from any nearby power lines or line cords located in and around buildings and homes. From the high-pass filter, the signal is applied to transistor Ql (which provides a 10-dB gain for frequencies in the 1- to 2000-MHz range) for amplification. Resistors R2, R3, and R4 form the biasing network for Ql. The amplified signal is then ac coupled, via capacitor C4 and resistor R7`s (the sensitivity control) wiper, to the inverting input (pin 2) of Ul-a. Op amp Ul-a is configured as a very high gain amplifier.
Bug Detector Circuit - schematic

With no signal input from ANT1, the output of Ul-a at pin 1 is near ground potential. When a signal from the antenna is applied to the base of Ql, it turns on, producing a negative-go-ing voltage at the cathode of Dl. That voltage is applied to pin 1 of Ul-a, which amplifies and inverts the signal, producing a positive-going output at pin 1. Op amps Ul-b and Ul-c along with 08, RIO through R18, and Q2 are arranged to form a voltage-controlled oscillator (VCO) that operates over the audio-frequency range. As the output of Ul-a increases, the frequency of the VCO increases, The VCO output, at pin 8 of Ul-c, is fed to the input of Ul-d, which is configured as a noninverting, unity-gain (buffer) amplifier. The output of Ul-d is used to drive Q3, which, in turn, drives the output speaker.




Leave Comment

characters left:

New Circuits

.