Grand Prix Starting Lights

This circuit replicates the starting light sequence currently utilized by FISA for Formula One racing. It can be applied to slot car sets (such as HO scale AFX/Life Like/Tyco sets) or radio-controlled cars. IC1, a 555 timer integrated circuit, functions as a clock pulse generator. Its output is routed through NAND gates IC2a and IC2c to IC3, a 4024 binary counter. IC2b inverts the O4 output of the 4024 binary counter IC3. Initially, IC3 is reset, resulting in all its outputs being low, including O4, which causes IC2b to present a logical high to the pin 8 input of IC2c. This allows pulses from the 555 clock circuit to be passed to the clock input of the 4024. IC3 then begins counting. Once the count reaches binary 1111, the next pulse sends the O4 output of IC3 high, disabling IC2c and stopping IC3 from counting. The four outputs of IC3 are connected to a resistor ladder, functioning as a simple digital-to-analog converter (DAC). As the count increases, the voltage produced at the top of the ladder rises, which is connected to the inverting inputs of four comparators within IC4 (an LM339) and to IC5, a 741 operational amplifier also configured as a comparator. The positive inputs of the comparators are connected to the taps of a voltage divider, with the tapping voltages adjusted using VR1, a 100kΩ trimpot. As IC3 counts, the rising stepped voltage from the DAC ladder sequentially activates the comparators, starting with IC4d and progressing to IC5. As each comparator is activated, its corresponding pair of LEDs is illuminated; first LEDs 1 & 2, then LEDs 3 & 4, and so forth. When all five pairs of LEDs are lit, the subsequent pulse from IC1 advances the binary count of IC3 to 10000, causing the DAC voltage to drop back to zero and extinguishing all LEDs. Simultaneously, counting ceases because the high signal on O4 prevents further gate pulses from IC2c. The circuit remains inactive until it is reset by pressing pushbutton switch S1, allowing a new sequence to commence.

The circuit operates as a visual indicator for the start of a race, effectively simulating the light sequence seen in actual Formula One events. The 555 timer IC is configured in astable mode, generating a continuous square wave output that serves as the clock signal. The NAND gates are used to ensure proper signal conditioning, allowing the binary counter to count accurately without glitches. The 4024 binary counter, which counts in binary, provides a straightforward means of tracking the sequence of lights.

The resistor ladder's design allows for a gradual increase in voltage corresponding to the binary count, effectively translating digital signals into an analog voltage. This voltage is crucial for the comparators, which are set to specific thresholds determined by the voltage divider. The use of a trimpot enables fine-tuning of the comparator thresholds, allowing for precise control over when each LED pair is illuminated.

The operational amplifier configured as a comparator enhances the circuit's functionality by providing an additional output that can be used for further control or signaling purposes. The sequential activation of LED pairs not only serves as a visual countdown but also adds an engaging element to the operation of slot car sets or radio-controlled vehicles.

The reset functionality via pushbutton switch S1 ensures that the circuit can be easily restarted for subsequent races or demonstrations, making it suitable for both casual and competitive settings. Overall, this circuit exemplifies an effective integration of digital and analog components to achieve a dynamic and visually appealing result.This circuit reproduces the starting light sequence currently used by FISA for Formula One racing. It could be used with slot car sets (such as HO scale AFX/Life Like/Tyco sets) or radio controlled cars. IC1, a 555 timer IC, is used as a clock pulse generator. Its output is fed via NAND gates IC2a and IC2c to IC3, a 4024 binary counter. IC2b inver ts the O4 output of 4024 binary counter IC3. Initially, IC3 is reset and all its outputs are low, including O4, which causes IC2b to present a logical high to the pin 8 input of IC2c which then passes pulses from the 555 clock circuit to the clock input of the 4024. IC3 then begins counting. After the count has reached binary 1111, the next pulse sends the O4 output of IC3 high, which disables IC2c and IC3 stops counting.

The four used outputs of IC3 are connected to a resistor `ladder` which acts as a simple digital to analog convert-er (DAC). As the count increases so does the voltage produced at the top of the ladder and this is connected to the inverting inputs of four comparators inside IC4 (an LM339) and to IC5, which is a 741 op amp also connected as a comparator.

The positive inputs of the comparators are connected to the taps of a voltage divider, with the tapping voltages set using VR1, a 100kO trimpot. As IC3 counts, the rising stepped voltage from the DAC ladder switches the comparators on in sequence, starting with IC4d and working up to IC5.

As each comparator is turned on, its pair of LEDs is lit; first LEDs 1 & 2, then LEDs 3 & 4 and so on. When all five pairs of LEDs are lit, the next pulse from IC1 moves the binary count of IC3 to 10000, so the DAC voltage drops back to zero and all LEDs are extinguished.

At the same time, counting also stops, because the high on O4 causes IC2c to block further gate pulses. The circuit then remains inactive until the counter is reset by pressing pushbutton switch S1. This allows a new sequence to begin. 🔗 External reference