MFOS Micro-Sample & Hold circuit

The voltage to be sampled is applied to the input of R2, a 100K linear taper potentiometer, while the other end of R2 is grounded. Consequently, the signal level that is sent to the buffering level shifter U1-A and its associated components is determined by R2. The signals applied to the sample and hold circuit at point X1 can fluctuate around ground but should not exceed approximately ±5.5 volts. To accommodate higher signal levels, the design was modified to allow for attenuation through R2. If the voltage at pin 1 of U1-A drops below ground, Q1 can clip the signal, leading to improper sampling. R1 and R3 form a voltage divider, effectively reducing the attenuated signal to half its original level. This signal is then fed into U1-A (1/4 LF444 quad op amp), where it is level-shifted and amplified by a factor of about 1.5. A comparison can be made between the input signal and the signal at pin 1 of U1-A. The Q1 N-Channel JFET 2N5457 functions as a closed switch between its source and drain when its gate is slightly elevated above ground by differentiated pulses generated from the leading edge of the rectangular wave output by U1-D, the sample clock generator. When no pulse is applied, the gate of Q1 is maintained at approximately -3.6V by a resistor network consisting of R7, R6, and R13. The voltage present at the source of Q1 passes through to the drain, charging or discharging C1, which holds the sampled voltage until the next pulse arrives at the gate. U1-B buffers the voltage held on the capacitor. The LF444CN chip features ultra-low input current, enabling the sample to remain on the capacitor and be buffered by U1-B for an extended period. In the absence of a pulse at the gate of Q1, it behaves like an open switch, preventing any leakage of voltage from C1 through the transistor. Buffer U1-B provides a gain of approximately 1.5 and also level shifts the signal to closely match the original input level, oscillating around ground. This represents the sampled and held voltage (blue) in comparison to the input voltage (yellow), with an evident level shift reflecting the actual input signal level. The differentiated pulse applied to the gate of Q1 via C4, in series with R6, indicates that Q1's source to drain effectively acts as a closed switch during the pulse. The output varies during the pulse as a new sample is acquired. The sample clock generator U1-D and its associated components operate as follows: assuming the output of U1-D has just transitioned low (to about -11V), the voltage at U1-D pin 12 is approximately -1.9 volts. C8 (10uF aluminum or tantalum electrolytic capacitor), which was previously charged (U1-D was high before this transition) to above ground (around 2V), begins to discharge through R15 and the 1M Sample Rate adjust potentiometer R16. When C8 discharges below -1.9 volts (the level at pin 12), the output of U1-D jumps to about +11V, raising the voltage at U1-D pin 12 to about +1.9V, and causing C8 to charge from its previous voltage (approximately -2V) towards V+ through D2 (1N914 high-speed diode) and R15 (4.7K resistor). Once C8 charges to a level exceeding that of U1-D pin 12 (around +2V), the output of U1-D drops low again, and this cycle continues. The output from U1-D produces an asymmetric rectangular pulse wave due to D2, which allows the positive excursion of U1-D to charge C8 without interference from the 1M Sample Rate potentiometer R16. Consequently, the high time is limited to about 20 ms, while the low time is adjustable based on the setting of the 1M Sample Rate potentiometer R16. The sample clock rate can vary from approximately 0.33 hertz to 30 hertz. The sample clock output is directed through D3 (1N914) and dropped across R18 (100K resistor) before being connected to the trigger output jack. These signals are observed at the inputs of U1-D, with the blue waveform representing the charge and discharge of C8 at U1-D pin 13.

The circuit described encompasses a sample and hold system, which is critical in analog-to-digital conversion processes. The use of a potentiometer (R2) allows for the adjustment of input voltage levels, ensuring compatibility with the operational amplifier (U1-A) and preventing clipping by the JFET (Q1). The voltage divider formed by R1 and R3 is essential for scaling the signal appropriately before amplification and level shifting, which is crucial for maintaining signal integrity.

The JFET (Q1) operates as a switch, controlled by the sample clock pulses generated by U1-D, allowing precise timing in capturing the input signal's voltage. The capacitor (C1) serves as the storage element for the sampled voltage, which is buffered by U1-B to maintain signal fidelity over time. The LF444 op-amp's low input current characteristic is advantageous for minimizing leakage and ensuring that the sampled voltage remains stable during the hold phase.

The sample clock generator (U1-D) is integral to the operation of the sample and hold circuit, providing the necessary timing signals to control the sampling process. The asymmetric rectangular wave output ensures that the capacitor can charge efficiently while allowing for adjustable sample rates, accommodating various application requirements. The overall design emphasizes precision in sampling and holding voltages, which is fundamental for accurate signal processing in electronic systems.Voltage to be sampled is applied to the input which is one end of R2 (100K linear taper potentiometer). The other end of R2 is grounded and thus the level of signal applied to buffering level shifter U1-A and associated components is controlled by R2.

Signals applied to the sample and hold (at point X1) can oscillate about ground but should not exceed about +/-5. 5 volts. That is why the design was changed to allow for higher level signals since they can be attenuated by adjusting R2. If the voltage at pin 1 of U1-A goes below ground Q1 can clip the signal and improper sampling results.

R1 and R3 comprise a voltage divider which causes the applied attenuated signal to be effectively cut down to half of it`s level. This signal is applied to U1-A (1/4 LF444 quad op amp) where it is level shifted and given a gain of about 1.

5. Here you can see the comparison of the input signal to the signal at pin 1 of U1-A. Q1 N-Channel JFET 2N5457 acts like a closed switch (between source and drain) when it`s gate is brought slightly above ground by differentiated pulses which are generated by picking off the front end of the rectangle wave output by U1-D sample clock generator. Normally (when no pulse is being applied) the gate of Q1 is held at about -3. 6V by resistor network R7, R6 and R13. The voltage that is present at the source of Q1 passes through to the drain and charges (or discharges as the case may be) C1 where the sampled voltage is held until the next pulse hits the gate.

U1-B buffers the sample held on the cap. The LF444CN chip has ultra low input current which allows the sample to sit on the cap and be buffered by U1-B for quite some time. With no pulse applied to the gate of Q1 it essentially acts like an open switch (source to drain) and the voltage on C1 does not leak back through the transistor.

Buffer U1-B applies gain of about 1. 5 and also level shifts the signal so that it approximates the original input level and oscillates about ground. This is the sampled and held voltage (blue) as it compares to the input voltage (yellow). Notice the level is shfted so that it reflects the actual input signal level. This is the differentiated pulse that is applied to the gate of Q1 via C4 in series with R6. Q1 source to drain is essentially a closed switch during the pulse. The output changes during the pulse as a new sample is acquired. Sample clock generator U1-D and associated components works as follows. If we begin our analysis imagining that the output of U1-D just went low (to about -11V) we see that the voltage level applied to U1-D pin 12 is about -1.

9 volts. C8 (10uF aluminum or tantalum electrolytic capacitor) which had previously been charged (remember U1-D just went low and was high prior to that transition) to well above ground (actually to about 2V) begins to discharge via R15 and 1M Sample Rate adjust pot R16. When C8 discharges to below -1. 9 volts (the level on pin 12 remember) the output of U1-D shoots to about +11V causing the voltage at U1-D pin 12 to go to about +1.

9V and also causing C8 to charge from it`s previous voltage (about -2V) towards V+ via D2 (1N914 high speed diode) and R15 (4. 7K resistor). When C8 charges to above the level on U1-D pin 12 (about +2V), U1-D`s output shots low again and this cycle continues.

The output of U1-D is an asymmetric rectangular pulse wave due to D2 which allows the positive excursion of U1-D to charge C8 without the effect of 1M Sample Rate pot R16. Thus the high time is limited to about 20 mS and the low time depends on the setting of 1M Sample Rate pot R16.

The rate of the sample clock can be varied from about 0. 33 hertz to about 30 hertz. The sample clock`s output is fed through D3 (1N914) and dropped on R18 (100K resistor) and then connected to the jack for the trigger output. These are the signals observed on the inputs of U1-D. The blue waveform is the charge and discharge of C8 on U1-D pin 13. The 🔗 External reference