Pulse Generator circuit

A simple pulse generator with a variable duty cycle and frequency is often useful in the lab to trigger or test other devices, such as a servo with a frequency of 50 Hz and pulses between 1 and 2 ms. The project was initiated with this concept, but it was determined that it was not suitable for the intended application. The duty cycle of Timer1 can be calculated using the formula D = (OCR1A + 1) / (OCR1C + 1), where the PWM frequency is given by fpwm = 1 / (OCR1C + 1). Consequently, the duty cycle D can also be expressed as D = fpwm * (OCR1A + 1). This calculation is performed in the Basic programming language. The frequency can be set while maintaining a constant duty cycle, such as 50% or any other desired percentage. The duty cycle scale is linear, but the frequency scale is hyperbolic, which presents a limitation, with a maximum practical frequency setting of approximately 1 MHz. The frequency and duty cycle are independently controlled by two potentiometers read by two ADCs in a loop. The controller operates on an internal 8 MHz system clock (with the CKDIV8 fuse unprogrammed) and utilizes a fast PLL clock for Timer1, which runs at 8 times the system clock frequency. The PLL must be enabled and requires some time to lock in before Timer1 can operate at a clock frequency of 64 MHz. A single pushbutton is used to toggle between the PLL clock and the system clock, while another pushbutton cycles through Timer1 prescaler values from 1 to 15 and back to 1. The main program is written in Basic, while the portion handling the PLL is implemented in assembly language. This pulse generator is digital and utilizes 8-bit PWM, which introduces some granularity when adjusting the potentiometers, potentially limiting its application. For instance, with the system clock and a prescaler of 2048, Timer1 receives one clock pulse every 512 microseconds, establishing a resolution limit where the duty cycle step width is also 512 microseconds. Thus, it is not feasible to achieve a 1 microsecond pulse width at a frequency of 50 Hz.

The pulse generator circuit utilizes an Atmel microcontroller, which is programmed to generate PWM signals with adjustable frequency and duty cycle. The circuit comprises a Timer1 module that is crucial for PWM generation. The output compare registers, OCR1A and OCR1C, are configured to set the duty cycle and frequency, respectively. The duty cycle is calculated based on the values in these registers, allowing for a flexible range of output characteristics.

The system clock operates at 8 MHz, and the PLL boosts the clock frequency to 64 MHz, enabling high-speed operations. The use of potentiometers allows for user-friendly adjustments of frequency and duty cycle, with the ADCs converting the analog voltage from the potentiometers into digital values that the microcontroller can process. The linear relationship of the duty cycle with respect to the output compare register values enables straightforward control, while the hyperbolic nature of frequency adjustments necessitates careful calibration for optimal performance.

The circuit includes debouncing mechanisms for the pushbuttons used to toggle the clock source and change prescaler settings, ensuring stable operation. The assembly language component of the program manages the PLL configuration, ensuring that the system can switch between clock sources without glitches. Overall, this pulse generator circuit offers a versatile solution for generating PWM signals for various laboratory applications, although it is constrained by the inherent limitations of the timer resolution and frequency scaling.A simple pulse generator with a variable duty cycle and frequency is often useful in the lab to trigger or test other devices, e. g a servo with a frequency of 50 Hz and pulses between 1 and 2 ms. This is where the project started but for reasons we see later this idea was good but just not in this case.

How is it done From the Atmel datasheet we see that the duty cycle of Timer1 is basically D = (OCR1A+1) / (OCR1C+1). The PWM frequency is fpwm = 1 / (OCR1C+1). So the duty cycle D = fpwm * (OCR1A+1). This is calculated in the Basic program. We can set the frequency and keep the duty cycle constant at e. g 50% or any other percentage when the frequency is changed. The duty cycle D scale is linear but the frequency scale is not linear, bad luck it`s hyperbolic as with most analog frequency generators, so the upper convenient frequency setting is at about 1 MHz. The frequency and duty cycle are set independently by reading 2 potentiometers with 2 ADC in a loop. The controller uses an internal 8Mhz system clock (unprogram fuse CKDIV8) and also a fast PLL clock for Timer1 at 8 times the system clock.

The PLL must be enabled and takes some time to lock, then Timer1 can run on a 64 MHz clock frequency. It takes now 1 pushbutton to toggle between PLL clock and system clock, one more pushbutton walks through the Timer1 prescaler values between 1 and 15 and back to 1 and so on.

The main program is in Basic and the part dealing with the PLL is in assembler. It`s digital and it`s 8 bit pwm so it has some granularity when you turn the potentiometers which may be a limitation or not, depends on the application. As an example, with the system clock and clock/2048 for the prescaler the Timer1 will then get one clock pulse every 512 usec, that is the limit for the resolution, in other words, the duty cycle step witdh is 512 usec in this case.

No way to get a 1 usec pulse width at a frequency of 50 Hz. 🔗 External reference