Clock Circuits

The Clock Controller was designed to be an exemplary of using 'C' language to control timer0interrupt, 7-segment LED and keypad scanning. It provides 1-bit sink currentdriving output, for driving a relay, opto-triac, say. Many projects requiring7-segment display and keypad interfacing may get the idea from the Clockcircuit and software.

This simple counter can be used to count pulses, as the basis for a customer counter (like you see at the doors of some stores), or for anything else that may be counted. The circuit accepts any TTL compatible logic signal, and can be expanded easily (see Notes).

Serial-data systems often generate an internal clock at twice the data rate for mid-bit sampling or for generating bi-phase codes. External equipment and some internal processes require a clock that runs at the data rate.

The purpose of this application note is to design a clock while multiplexing the features as much as possible, allowing the circuit to use the 18-pin PIC16C54. Other devices in the Microchip line expand on this part, making it a good starting point for learning the basics.

A week or 3 ago I posted a question about reccomendations for building a simple clock doubling circuit, to operate at approx 500kHz, using CMOS logic. The circuit functions quite well and is stable. If the Not gates are omitted, however, it becomes unstable, and gives variable width pulses.

The simple, inexpensive circuit in Fig 1 provides backup power to a clock IC during outages. The circuit also determines whether the outage caused any loss in the time setting. C1provides the backup power, and the µC's ADC reads the time after the outage.

The oscillator circuit is one of the most overlooked areas of microprocessor circuit design. Components are usually selected based on the manufacturers? tables. If the circuit starts up and works, fine, no other thought need be given to it, right? Wrong. Many conditions can negatively affect the performance of your design.

The circuit uses a serial-in-parallel out shift register, 74HC595 for receiving serial data from uController board. See example of U5 in the schematic, SER is for data input, SRCLK is shift clock and RCLK is Latch clock. Each data bit is shifted into the register on rising edge of the shift clock. When all data bits are shifted into the 8-bit register, the rising edge of RCLK will clock the data to be latched at each output bit, i.e. QA - QH.

A motor spins the "propeller", and a small microprocessor keeps track of time and changes the pattern on seven LEDs with exact timing to simulate a 7 by 30 array of LEDs. It is an illusion, but it works nicely.

About every year I design and build a new clock. This year’s project is a clock based on an Intel 8008 first generation 8 bit microprocessor. Because it is a fairly unique project I’m putting more effort into the documentation. I’m also totally opening the design, hardware and software, to anyone wanting to learn more about the 8008.

This circuit has worked for me in many applications. (it might be an idea to buffer the signal befor using it. (There are still 5 unused gates in the 'C14.. :-)

In theory, synchronous clock multiplication is an easy task. A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator) and the second one placed directly at the input of the phase detector—may do the job. The flexibility of such a configuration allows for clock multiplication by any rational number.

The input-clock signal serves as the clock signal to a D flip-flop, which is configured as a toggle flip-flop. The flip-flop's output signal is thus a 50%-duty-cycle, half-frequency version of the input clock, independent of the input-clock duty cycle. The flip-flop's output passes through the clock-doubler circuit (from the earlier Design Idea, Figure 1b).

A common design need is to detect the presence or absence of a clock signal. In the absence of a clock, it may be necessary to switch to an alternate clock or to at least notify the system that a failure has occurred. The circuit in Figure 1 uses a silicon delay line to anticipate when the next clock cycle is due and makes the flip-flop sample the input clock to verify that a pulse is present.

A clock-recovery architecture can operate with NRZ digital signals, even at low SNRs. A clock-recovery subsystem is based on a PLL comprising a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO).

Many of today's digital systems require multiple clock domains as well as the ability to switch between them on the fly without producing glitches. Listing 1 consists of synthesizable VHDL code for such a circuit. In the circuit, two lines choose from among four input clocks to produce an output clock.

What is the effect of crosstalk from the digital data signals into the clock signal of a data-conversion system? This is a more obscure problem than crosstalk from digital bits into the analog signal path, which was the subject discussed in the previous article: Part 1 of this series, Effects of Digital Crosstalk in Data Converters.

Designed for monitoring charge and discharge current in secondary batteries, IC1 outputs a current of 0.5 mA per amp of load current flowing through its internal sense resistor while rejecting common-mode supply-voltage noise. The on-chip sense resistor handles as much as 3A of continuous current.

Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%. A limited range of available delays (2 to 100 nsec per tap) further limits their use. Longer delay is available with one-shot multivibrators of standard digital-logic families, but those devices do not retain duty-cycle information.

Timing delays are undesirable in most digital circuits. However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example. The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler. Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock.