Delay Circuits

The time delay for the common emitter will be approximately 3 time constants or 3*R*C. The capacitor/resistor values can be worked out from the relay coil current and transistor gain. For example a 120 ohm relay coil will draw 100 mA at 12 volts and assumming a transistor gain of 30, the base current will be 100/30 = 3 mA. The voltage across the resistor will be the supply voltage minus two diode drops or 12-1.4 = 10.6. The resistor value will be the voltage/current = 10.6/0.003 = 3533 or about 3.6K. The capacitor value for a 15 second delay will be 15/3R = 1327 uF. We can use a standard 1000 uF capacitor and increase the resistor proportionally to get 15 seconds.

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Lately, designers have been inserting negative-temperature-coefficient thermistors in series with some loads, such as switch-mode power supplies. This device presents a high resistance at the instant of switching, thus limiting the inrush current. After a few cycles, the resistance of the thermistor drops to a low value, allowing normal operation of the load. In contrast, the circuit in Figure 1 physically inserts a resistor in series with the load to limit the inrush current and then short-circuits the resistor after a time delay.

Figure 1 shows the outputs of one such current CCD driver, Intersil's EL7212 (www.elantec.com), with a dual-phase input clock. The overlap in the output stems from the turn-on and -off delay mismatches of the EL7212. In a low-resolution system with a lower clock frequency, the delay mismatch is an insignificant part of the clock period. As CCD scan rate increases, the mismatch becomes a large part of the clock period. You need a new approach to correct the CCD-driver delay mismatch. Figure 2 shows a circuit that uses amplifiers to sense the delay mismatch and correct it.

Here's a power-on time delay relay circuit that takes advantage of the emitter/base breakdown voltage of an ordinary bi-polar transistor. The reverse connected emitter/base junction of a 2N3904 transistor is used as an 8 volt zener diode which creates a higher turn-on voltage for the Darlington connected transistor pair. Most any bi-polar transistor may be used, but the zener voltage will vary from about 6 to 9 volts depending on the particular transistor used.

The AD8055-based amplifier has greater-than-100-MHz bandwidth, fully adequate for the 10-MHz oscilloscope. Its input impedance is 1 MΩ in parallel with 30 pF to match the oscilloscope's input and its low-capacitance probes. Figure 2b shows the final eye pattern, using the amplifier, the two-stage equalizer, and the 750-nsec delay cable. This pattern is essentially identical to the eye pattern that ensues using the oscilloscope without the circuit in Figure 1, except for the 750-nsec temporal shift.

When activated by pressing a button, this time delay relay will activate a load after a specified amount of time. This time is adjustable to whatever you want simply by changing the value of a resistor and/or capacitor. The current capacity of the circuit is only limited by what kind of relay you decide to use.

Using a more precise delay line, the circuit can output a triple clock (Figure 1b). The MSD1000 series of silicon delay lines from Maxim Integrated Products (Sunnyvale, CA) provides 5- to 500-nsec delays with nominal accuracies of ±5%. The manufacturer can also customize standard delays to meet special needs.

As an example, a PWM control circuit (Figure 1) must handle relatively long delays while retaining information about the input duty cycle. The upper half of this dual-path, precision one-shot works on the input signal's rising edge. The rising edge triggers the D flip-flop, IC3A, to drive IC4A's input low. IC4A has an open-drain output; the output therefore rises exponentially according to the single R1C1 time constant. IC1A compares the output with a dc voltage equal to 67% of VCC, producing a conveniently scaled delay equal to R1C1.

The 14001 (or 4001) CMOS gate here is configured as a simple digital inverter. Its output is fed to the base of a regular 2N3906 (PNP) transistor, Q1, at the junction of resistor R5 and capacitor C2. The input to IC1 is taken from the junction of the time-controlled potential divider formed by R2 and C1. Before power is applied to the circuit, C1 is fully discharged. Therefore, the inverter input is grounded, and its output equals the positive supply rail; Q1 and RY1 are both off under this circuit condition. When power is applied to the circuit, C1 charges through R2, and the exponentially rising voltage is applied to the input of the CMOS inverter gate.

This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer. Should the computer fail to send a pulse, the output changes state. The time can easily be set from seconds to hours.

Figure 1 shows the implementation of a small pulse generator. The operating principle of the circuit lies in applying two '1' levels to the AND-gate input before the delay line switches high. Figure 2 shows the signals associated with the circuit in Figure 1. Figure 3 shows a typical application circuit for the one-shot multivibrators. You can use IsSpice4 or PSpice to simulate this sample/hold circuit. Figure 4 shows the waveforms associated with the circuit in Figure 3

This circuit waits for a set time and then activates a relay. With the cap that is in the schematic you will get about a 6 sec delay till power on. You can change the cap in this circuit to 470uF for about a 20 sec delay.

Phone calls over satellite circuits experience a Ό-sec transmission delay in each direction. The low-cost circuit (around $20) in Fig 1a simulates this delay and provides hooks for inserting noise, echo, and other impairments. Designers debugging modems, fax machines, and other communication equipment can use this circuit to troubleshoot handshake timing and connection problems caused by transmission delays.

This is an unusual design in that it uses plain metal gate CMOS logic instead of the usual PIC or a custom chip. The 22uF capacitor charges up during one half of the ac cycle, and supplies trigger current to the triac on both halves.

Transient overloads are not short circuits but can push the power supply above its nominal load value. This scenario occurs with typical loads such as printer heads and small motors. When facing such a load profile, the power supply can easily trigger its protection circuit, especially if the open-loop gain is high. You will see any decrease in the output voltage on the primary side as a loss of feedback current, because the controller cannot keep the voltage constant.

The circuit in Figure 1a overcomes this typical Spice problem. The input clock drives two delay lines that feature the same specifications. When the clock goes high, one input to X2's AND gate is also high. However, because of the delay line, the other input stays low for the given dead time. When both inputs are high, the output is a logic one (Figure 1b).

The Sallen-Key realization of a 5.25-MHz, three-pole Butterworth filter has a gain of 2V/V and can drive 75Ω back-terminated coax with an overall gain of 1 (Figure 1). Used to reconstruct component-video (Y, Pb, Pr) and RGB signals, this filter has an insertion loss greater than 20 db at 13.5 MHz and greater than 40 db at 27 MHz (Figure 2). Like the antialiasing filter before an ADC, this filter removes the higher frequency replicas of a signal following a DAC.

A time delay relay is a relay that stays on for a certain amount of time once activated. This time delay relay is made up of a simple adjustable timer circuit which controls the actual relay.

For numerous applications, flat group delay (linear phase) is necessary to maintain system performance. The common group-delay equalizer of Fig 1a has unity gain and is a popular way to equalize data filters or alias filters when phase compensation is necessary. The alternative equalizer of Fig 1b, however, can provide a gain greater than one for systems that require additional gain (and when providing that gain elsewhere is impossible or impractical).